Photolithography processes for manufacturing semiconductor devices and liquid crystal displays (LCD's) generally coat a resist on a substrate, expose the resist coating to light to impart a latent image pattern, and develop the exposed resist coating to transform the latent image pattern into a final image pattern having masked and unmasked areas. Such a series of processing stages is typically carried out in a coating/developing system having discrete heating sections, such as a pre-baking unit and a post-baking unit. Each heating section of the coating/developing system may incorporate a hot plate with a built-in heater of, for example, a resistance heating type.
Feature sizes of semiconductor device circuits have been scaled to less than 0.1 micron. Typically, the pattern wiring that interconnects individual device circuits is formed with sub-micron line widths. Consequently, the heat treatment temperature of the resist coating should be accurately controlled to provide reproducible and accurate feature sizes and line widths. The substrates or wafers (i.e., objects to be treated) are usually treated or processed under the same recipe (i.e., individual treatment program) in units (i.e., lots) each consisting of, for example, twenty-five wafers. Individual recipes define heat treatment conditions under which pre-baking and post-baking are performed. Wafers belonging to the same lot are heated under the same conditions.
According to each of the recipes, the heat treatment temperature may be varied within such an acceptable range that the temperature will not have an effect on the final semiconductor device. In other words, a desired temperature may differ from a heat treatment temperature in practice. When the wafer is treated with heat beyond the acceptable temperature range, a desired resist coating cannot be obtained. Therefore, to obtain the desired resist coating, a temperature sensor is used for detecting the temperature of the hot plate. On the basis of the detected temperature, the power supply to the heater may be controlled with reliance on feedback from the temperature sensor. However, because the temperature of the entire hot plate is not uniform and varies with the lapsed time, it is difficult to instantaneously determine the temperature of the hot plate using a single temperature sensor.
The post exposure bake (PEB) process is a thermally activated process and serves multiple purposes in photoresist processing. First, the elevated temperature of the bake drives the diffusion of the photoproducts in the resist. A small amount of diffusion may be useful in minimizing the effects of standing waves, which are the periodic variations in exposure dose throughout the depth of the resist coating that result from interference of incident and reflected radiation. Another main purpose of the PEB is to drive an acid-catalyzed reaction that alters polymer solubility in many chemically amplified resists. PEB also plays a role in removing solvent from the wafer surface.
Chemical amplification allows a single photoproduct to cause many solubility-switching reactions, thus increasing the sensitivity of these photoresist systems. Some amount of acid transport is necessary in that it allows a single acid to move to many reactive polymer sites. However, acid transport from nominally exposed to unexposed regions can complicate control of resist feature dimensions. Acid transport through these reactive systems is mechanistically complex. Measurements have shown that there is a very large difference in acid mobility between the starting material, which is reactive towards acid, and the product material, which is no longer reactive.
In addition to the intended results, numerous problems may be observed during heat treatment. For example, the light sensitive component of the resist may decompose at temperatures typically used to remove the solvent, which is a concern for a chemically amplified resist because the remaining solvent content has a strong impact on the diffusion and amplification rates. Also, heat-treating can affect the dissolution properties of the resist and, thus, have direct influence on the developed resist profile.
With the continued shrink of critical dimensions (CD) and allowable critical dimension non-uniformities (CDU) and the continued use of chemically amplified resist (CAR), the post exposure bake (PEB) process contributes to a very large portion of the overall CDU budget. Historically the post exposure bake has been accomplished with a single bake with a thermal profile similar to that of FIG. 1 in which the processing wafer will come into the bake at ambient temperature 50 and go through a ramp up profile 52 to bring it to or very near a requested process temperature 54. Contemporary processes may go from an ambient temperature of about 23° C. to a process temperature of about 100-130° C. The final target temperature depends on resist chemistry. The bake profile would then have a stage 56 during the baking process that was basically thermally stable, typically referred to as steady state, until the overall requested processing time was complete at which time the wafer would be exchanged to a cooling arm or cool plate and the wafer would experience a rapid thermal ramp down 58 back to or near ambient temperature. Because the baking process is being applied over a large wafer area, a large thermal gradient, and partially because hot plates are generally multi-zoned, with multiple heating elements and with individual sensors and controllers for each zone, there is an inherent across wafer thermal variation associated with the bake process. With contemporary hot plate zone control schemes, the speed at which the thermal ramp 52 is attempted directly relates to the peak magnitude of variation, the broadness of the variation distribution, and also the total integrated area of variation. The choice of ramp up condition therefore becomes a balance of applying enough thermal energy to exhaust the chemically-amplified reaction without having a thermal variation profile through time that generates a high hot plate induced CD non-uniformity.
In the above application, the hot plate controller(s) tries to keep the variation experienced at each moment in time, through ramp up and steady state, to a minimum on the hot plate. There is an assumption that all hot plate variation through time is equivalent or at least that all hot plate variation through time above the activation energy of the chemically activated resist is equivalent. In reality, since chemically amplified resist reaction rates adhere to an Arrhenius relationship described by the equation below and as seen in the graph in FIG. 2,
      ln    ⁡          (      k      )        =                              -                      E            α                          R            ⁢              1        T              +          ln      ⁡              (        A        )            in which the reaction rate increases exponentially with temperature above the activation energy, the variation experienced, for example, at a target temperature minus 10° C. is not equivalent to a variation experienced at the target temperature minus 3° C.
What is needed therefore is an apparatus and associated method for the post exposure bake that minimizes CD non-uniformity due to hot plate variation.